In the logic design phase of an LSI, verification of the LSI logic is critically important. This is because a serious logic defect, if detected after the logic design has been implemented in a chip, requires remaking the mask thereby increasing the fabrication cost and also the time required for the development of an LSI.
Logic simulation is prevalent in the industry and is used as the traditional technique for LSI logic verification. However, this technique has the following disadvantages:
(A) To verify LSI's having a large logic scale requires tremendous amounts of calculation time. PA1 (B) The calculation time is prolonged when time-consuming logic operations such as testing the communication of the LSI with a network is simulated. PA1 (C) It is practically impossible to produce an accurate software model for verifying the interface with the parts on a chip or with devices outside the chip.
One solution to the above deficiencies is provided by known logic emulation systems. A typical logic emulation system involves first developing the logic of the target LSI in programmable devices such as field programmable gate arrays (FPGA's). These programmable devices are connected directly or via intermediate tools either to the board on which the actual LSI is to be mounted or on a similar board. The result is a prototype of the logical device.
The programmable devices are devices which are prepared without preparation of a mask and to which users may write logic circuits. The procedure above makes it possible to provide at a low cost a verification environment close to the actual implementation. Some programmable devices also permit rewrite operations thereto. This means that they allow the logic inside to be corrected according to the results of the verification. Where the quality of the logic circuits is assured to a sufficient degree, they may be used to debug software.
FIG. 16 is a schematic view of a hardware configuration constituting a conventional logic emulation system. FIG. 16 shows: a storage medium in which the logic data 101 is stored regarding a target LSI; a workstation or a personal computer 102; a programmable device writer 103; field programmable gate arrays (called the FPGA's hereunder) 104; an emulation board 105; and a verification board 106.
From the logic data 101, the workstation or personal computer 102 prepares data to be programmed into the FPGA's 104 for the emulation. The programmable device writer 103 writes the program data thus prepared to the FPGA's 104. The types and the quantity of FPGA's 104 are determined depending on the scale of the LSI logic to be verified. The emulation board 105 on which the FPGA's 104 are mounted allows the on-board parts to be wired in a programmable manner. This means that dedicated programmable devices may be used as well.
The verification board 106 is equivalent to the board of the target logical device except that the emulation board 105, instead of the LSI, is connected to the verification board 106. The FPGA's 104 may be mounted directly on the verification board 106.
FIG. 17 is a flowchart of steps for emulation processing by a conventional logic emulation system. In step 201 of FIG. 17, an editor or like device is used to input the logic of the logic circuits. In step 202, the logic to be verified is divided into a plurality of FPGA's 104 if the logic cannot be accommodated in a single FPGA 104. In step 203, where the logic is described at the register transfer level, logic synthesis is carried out to map the logic in the programmable devices in use (e.g., FPGA's).
In step 204, the devices are wired and in step 205, the result of the wiring is programmed into the devices. In step 206, the devices are used for verification. In step 207, a check is made to see if any defect has occurred. If a defect is detected, the logic is corrected and the processing is repeated from the input of the logic. In step 208, logic verification is terminated and the verified logic is implemented in the target LSI such as gate arrays.